An adaptive frequency synthesizer architecture reducing reference sidebands

SEMI OpenIR > 中国科学院半导体研究所（2009年前）

	An adaptive frequency synthesizer architecture reducing reference sidebands
	Wang, HY (Wang, Haiyong); Shou, GL (Shou, Guoliang); Wu, NJ (Wu, Nanjian); Wang, HY, Beijing LHWT Microelectr Inc, Beijing, Peoples R China.
	2006
会议名称	IEEE International Symposium on Circuits and Systems
会议录名称	2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS丛书标题: IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS
页码	VOLS 1-11 PROCEEDINGS: 3081-3084
会议日期	MAY 21-24, 2006
会议地点	Kos Isl, GREECE
出版地	345 E 47TH ST, NEW YORK, NY 10017 USA
出版者	IEEE
ISSN	0277-674X
ISBN	978-0-7803-9389-9
部门归属	beijing lhwt microelectr inc, beijing, peoples r china; chinese acad sci, inst semicond, beijing 100083, peoples r china
摘要	An adaptive phase-locked loop (PLL) frequency synthesizer architecture for reducing reference sidebands at the output of the frequency synthesizer is described. The architecture combines two tuning loops: one is the main loop for locking the PLL frequency synthesizer and operating all the time, the other one is auxiliary loop for reducing reference sidebands and operating only when the main loop is closely locked. A 1.8V 1GHz fully integrated CMOS dual-loop frequency synthesizer is designed in a 0.18um CMOS process. The suppression of the reference sidebands of the proposed frequency synthesizer is 13.8dB more than that of the general frequency synthesizer.
关键词	Tuning System
学科领域	半导体物理
主办者	IEEE.
收录类别	CPCI-S
语种	英语
文献类型	会议论文
条目标识符	http://ir.semi.ac.cn/handle/172111/9860
专题	中国科学院半导体研究所（2009年前）
通讯作者	Wang, HY, Beijing LHWT Microelectr Inc, Beijing, Peoples R China.
推荐引用方式 GB/T 7714	Wang, HY ,Shou, GL ,Wu, NJ ,et al. An adaptive frequency synthesizer architecture reducing reference sidebands[C]. 345 E 47TH ST, NEW YORK, NY 10017 USA:IEEE,2006:VOLS 1-11 PROCEEDINGS: 3081-3084.

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